In fabrication of logic gates, particularly fabrication of RMGs using traditional RMG modules, topography of the resulting device is particularly important to performance, reliability, and a manufacturability of the device. Further, as technology has continued to allow for the fabrication of smaller technology nodes, the effects of topography variations have increased. However, topography variation, layer thickness variation, and defects are frequently caused by traditional RMG modules. For instance, during traditional RMG modules the gate etch causes topography variation. In another example, a metal chemical mechanical polishing (CMP) leaves metal residue causing the trench silicide and gate electrode to short and also causing a thickness variation in an exposed oxide formed by flow-controlled vertical deposition (FCVD). Additionally, high density plasma (HDP) deposition induces bubble defects in the oxide formed by FCVD. The resulting device using traditional RMG modules may contain topography variations exceeding 100 angstroms (Å), causing a degradation in performance, reliability, and a manufacturability, particularly in 20 nm technology nodes and beyond. Further, such variations in a single gate using traditional RMG modules may cause a gate height variation between gates that exceeds more than 200 Å, resulting in further degradation in performance, reliability, and manufacturability of the resulting device.
Efforts to mitigate such variations include, for instance, reducing the gate etching intensity. However, such a reduction results in degradation of the gate oxide quality. Additionally, a removal amount for CMP may be increased to reduce thickness variation in the oxide. However, such an increase may cause a high-K metal gate (HKMG) filling problem with a high aspect ratio. Further, the oxide layer formed by FCVD may be increased in thickness and the HDP deposition may be decreased to mitigate the bubble defect. However, such a modification may result in a high dishing caused by HDP CMP due to the exposure of the oxide, resulting in an increase in gate height variation.
A need therefore exists for methodology enabling fabrication of RMGs having a low gate variation and a substantially planar topography, and the resulting device.